This application claims the priority benefit of Taiwan application Ser. No. 9115996, filed on Aug. 9, 2000.
1. Field of Invention
The present invention relates to a cache system and method of operation for interfacing with peripheral devices. More particularly, the present invention relates to a two-way cache system and method of operation for interfacing with peripheral devices.
2. Description of Related Art
At present, the one-way cache system is the most common method for interfacing with peripheral devices. In a one-way cache system, the cache memory stores only the most recent batch of data read from a peripheral device. A batch of data in this type of cache memory is equivalent to a line of data or 32 bytes. Depending on actual conditions, the buffer area for holding the data ranges from two to eight lines. Hence, on receiving a read command, this type of cache system also pre-fetches a line of data besides reading out data required by the read operation. After sending out the needed portion in the first line of data to a peripheral device, data within the first data line is discarded. Only the pre-fetched data is retained, meaning that the data within the second data line is held in the buffer region.
However, not every one of the peripheral devices read data based on a data line. In other words, some peripheral devices may just need the front portion of the data within the first data line. Hence, after the front portion of the data is retrieved, the one-way cache system discards data in the first data line while retaining the second data line. When some other peripheral devices need to access the back portion of the data discarded by the cache system, the data must be read from memory again. After reading in the first data line anew, the previously stored data in the second data line is wiped out. If data in the second data line is needed again, the data has to be read from memory again. Such double reading not only decreases processing speed but also increases the number of data transmissions. Ultimately, a greater loading at the peripheral device interface may result, leading to a lower operating efficiency.
A solution is provided in U.S. Pat. No. 6,138,213, titled xe2x80x9cCache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line,xe2x80x9d by McMinn et al. In this patent, a cache employs one or more prefetch ways for storing prefetch cache lines and one or more ways for storing accessed cache lines. Prefetch cache lines are stored into the prefetch way, while cache lines fetched in response to cache misses for requests initiated by a microprocessor connected to the cache are stored into the non-prefetch ways. Accessed cache lines are thereby maintained within the cache separately from prefetch cache lines. When a prefetch cache line is presented to the cache for storage, the prefetch cache line may displace another prefetch cache line but does not displace an accessed cache line. A cache hit in either the prefetch way or the non-prefetch ways causes the cache line to be delivered to the requesting microprocessor in a cache hit fashion. The cache is further configured to move prefetch cache lines from the prefetch way to the non-prefetch way if the prefetch cache lines are requested (i.e. they become accessed cache lines). Instruction cache lines may be moved immediately upon access, while data cache line accesses may be counted and a number of accesses greater than a predetermined threshold value may occur prior to moving the data cache line from the prefetch way to the non-prefetch way. Additionally, movement of an accessed cache line from the prefetch way to the non-prefetch way may be delayed until the accessed cache line is to be replaced by a prefetch cache line.
Accordingly, one object of the present invention is to provide a two-way cache system and method of operation for interfacing with peripheral devices. The cache system is capable of downloading two sections of data in each reading so that utilization rate of the cache memory is increased and data transmission loading is lowered, thereby increasing overall performance of the peripheral device interface.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a two-way cache system for interfacing with a peripheral device. The two-way cache system is suitable for transmitting data between a peripheral device and a memory unit and includes a two-way first-in first-out (FIFO) buffer region and a two-way cache controller. The two-way first-in first-out (FIFO) buffer region includes a first cache data region and a second cache data region. The first cache data region is capable of holding a batch of first cache data. The second cache data region is capable of holding a batch of second cache data. The two-way cache controller is capable of receiving a read request from the peripheral device. According to the read request, the two-way first-in first-out buffer region retains a batch of requested data that meets the read request and a batch of ensuing data that comes after the requested data. In addition, the peripheral device enables a FRAME signal line continuously so that when data input continues to be requested, data is read one by one by alternating between the first cache data region and the second cache data region.
In one embodiment of this invention, a relatively complicated circuit but time saving operating method is used. The operating method includes checking whether the requested data is already present inside the two-way first-in first-out buffer region when the two-way cache controller receives the read request. If the requested data is within the first cache data region (the second cache data region), the two-way cache controller checks for coherence between the first cache data (the second cache data) and the data stored inside the memory unit.
If the data stored in the first cache (the second cache) and the data stored in the memory unit are non-coherent, the requested data is read out from the memory unit by the two-way cache controller. Newly read data is then stored to the first cache data region (the second cache data region). The second cache data (the first cache data) are next checked to see if the aforementioned batch of ensuing data is also included. If the second cache data (the first cache data) includes the batch of ensuing data, the second cache data (the first cache data) and the memory unit data are checked for coherence. If the second cache data (the first cache data) and the data in the memory unit are non-coherent, the batch of ensuing data is read from the memory unit and puts into in the second cache data region (the first cache data region). Furthermore, if the second cache data (the first cache data) does not include the ensuing batch of data, the batch of ensuing data is read from the memory unit into the second cache memory region (the first cache memory region).
When the first cache data (the second cache data) and the memory data are coherent, the two-way cache controller checks the second cache data (the first cache data) to see if the batch of ensuing data is also included. If the second cache data (the first cache data) includes the batch of ensuing data, the second cache data (the first cache data) and the data stored in the memory unit are checked for coherence. If the second cache data (the first cache data) and the data in the memory unit are non-coherent, the batch of ensuing data is read from the memory unit and put into the second cache data region (the first cache data region). Furthermore, if the second cache data (the first cache data) does not include the batch of ensuing data, the batch of ensuing data is read from the memory unit into the second cache data region (the first cache data region).
When the requested data is not included inside the two-way first-in first-out buffer region, the two-way cache controller reads out the requested data as well as the aforementioned batch of ensuing data from the memory unit. The requested data and the batch of ensuing data are put in sequence into the first cache data region and the second cache data region, respectively.
If the peripheral device keeps requesting input data (in other words, a FRAME enable signal is maintained) after the requested data is read, the two-way cache controller controls the data that comes after the second cache data to be read into the first cache data region and becomes a batch of first cache data when the peripheral device reads in the second cache data. When the peripheral device reads the first cache data, the data that comes after the first cache data is read from the memory unit into the second cache data region to become a batch of second cache data.
In another embodiment of this invention, the number of data comparisons is reduced through at most one additional reading operation. Hence, a simpler circuit than the aforementioned embodiment can be used. In this embodiment, only the requested data is compared. The batch of ensuing data is directly read from the memory unit without first making a hit-or-miss comparison between the ensuing data and data originally stored inside the two-way first-in first-out buffer region. Although an additional reading operation (reading the ensuing batch of data) is required with such an arrangement, execution rate at the peripheral device interface can still be improved. Moreover, since hit-or-miss comparisons are eliminated, there is no need for a hit-or-miss comparison circuit. That is why the circuit in this embodiment is simplified.
In brief, this invention utilizes a two-way cache system to improve the operating efficiency at the peripheral device interface. The method of operating the cache system is an improvement over the conventional cache system. In addition, the circuit used in this invention is less complicated compared with a conventional cache system.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.